View HM5112805FLTD-6_2810427.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hm5112805f-6, hm5113805f-6 128m edo dram (16-mword 8-bit) 8k refresh/4k refresh ade-203-1050c (z) rev. 3.0 feb. 2, 2000 description the hitachi hm5112805f, hm5113805f are 128m-bit dynamic rams organized as 16,777,216-word 8-bit. they have realized high performance and low power by employing cmos process technology. hm5112805f, hm5113805f offer extended data out (edo) page mode as a high speed access mode. they are packaged in 32-pin plastic tsopii. features single 3.3 v supply: 3.3 v 0.3 v access time: 60 ns (max) power dissipation ? active: 720 mw (max) (hm5112805f) 792 mw (max) (hm5113805f) ? standby : 3.6 mw (max) (cmos interface) : 1.8 mw (max) (cmos interface) (l-version) edo page mode capability refresh cycles ? ras -only refresh 8192 cycles/64 ms (hm5112805f) 4096 cycles/64 ms (hm5113805f) ? cbr/hidden refresh 4096 cycles/64 ms (hm5112805f, hm5113805f)
hm5112805f-6, hm5113805f-6 2 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh (l-version) battery backup operation (l-version) ordering information type no. access time package hm5112805ftd-6 60 ns 400-mil 32-pin plastic tsop ii (ttp-32df) HM5112805FLTD-6 60 ns hm5113805ftd-6 60 ns hm5113805fltd-6 60 ns
hm5112805f-6, hm5113805f-6 3 pin arrangement (hm5112805f) (top view) 32-pin tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc i/o0 i/o1 i/o2 i/o3 nc v cc we ras a0 a1 a2 a3 a4 a5 v cc v ss i/o7 i/o6 i/o5 i/o4 v ss cas oe a12 a11 a10 a9 a8 a7 a6 v ss pin description pin name function a0 to a12 address input ?row/refresh address a0 to a12 ?column address a0 to a10 i/o0 to i/o7 data input/output ras row address strobe cas column address strobe we write enable oe output enable v cc power supply v ss ground nc no connection
hm5112805f-6, hm5113805f-6 4 pin arrangement (hm5113805f) (top view) 32-pin tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc i/o0 i/o1 i/o2 i/o3 nc v cc we ras a0 a1 a2 a3 a4 a5 v cc v ss i/o7 i/o6 i/o5 i/o4 v ss cas oe nc a11 a10 a9 a8 a7 a6 v ss pin description pin name function a0 to a11 address input ?row/refresh address a0 to a11 ?column address a0 to a11 i/o0 to i/o7 data input/output ras row address strobe cas column address strobe we write enable oe output enable v cc power supply v ss ground nc no connection
hm5112805f-6, hm5113805f-6 5 block diagram (hm5112805f) timing and control timing and control column address buffers row address buffers i/o buffers a0 a1 to a10 a11 a12 i/o1 i/o3 i/o4 i/o6 ras cas we oe column decoder row decoder 16m array 16m array 16m array 16m array column address buffers row address buffers i/o buffers i/o0 i/o2 i/o5 i/o7 column decoder row decoder 16m array 16m array 16m array 16m array upper pellet lower pellet
hm5112805f-6, hm5113805f-6 6 block diagram (hm5113805f) timing and control timing and control column address buffers row address buffers i/o buffers a0 a1 to a10 a11 i/o1 i/o3 i/o4 i/o6 ras cas we oe column decoder row decoder 16m array 16m array 16m array 16m array column address buffers row address buffers i/o buffers i/o0 i/o2 i/o5 i/o7 column decoder row decoder 16m array 16m array 16m array 16m array upper pellet lower pellet
hm5112805f-6, hm5113805f-6 7 operation table ras cas we oe i/o 0 to i/o 7 operation h high-z standby l l h l dout read cycle ll l* 2 din early write cycle ll l* 2 h din delayed write cycle l l h to l l to h dout/din read-modify-write cycle lh high-z ras -only refresh cycle h to l l h high-z cas -before- ras refresh cycle l l h h high-z read cycle (output disabled) notes: 1. h: v ih (inactive), l: v il (active), : v ih or v il 2. t wcs 3 0 ns: early write cycle t wcs < 0 ns: delayed write cycle absolute maximum ratings parameter symbol value unit terminal voltage on any pin relative to v ss v t ?.5 to v cc + 0.5 ( 4.6 v (max)) v power supply voltage relative to v ss v cc ?.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w storage temperature tstg ?5 to +125 c dc operating conditions parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 v ss 000 v2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il ?.3 0.8 v 1 ambient temperature range ta 0 70 ?c notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm5112805f-6, hm5113805f-6 8 dc characteristics (hm5112805f) hm5112805f -6 parameter symbol min max unit test conditions operating current* 1, * 2 i cc1 200 ma t rc = min standby current i cc2 4 ma ttl interface ras , cas = v ih dout = high-z 1 ma cmos interface ras , cas 3 v cc ?0.2 v dout = high-z standby current (l-version) i cc2 500 m a cmos interface ras , cas 3 v cc ?0.2 v dout = high-z ras -only refresh current* 2 i cc3 200 ma t rc = min standby current* 1 i cc5 ?0ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 200 ma t rc = min edo page mode current* 1, * 3 i cc7 200 ma ras = v il , cas cycle, t hpc = t hpc min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 2.5 ma cmos interface dout = high-z cbr refresh: t rc = 15.6 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 1.6 ma cmos interface ras , cas 0.2 v dout = high-z input leakage current i li ? 5 m a 0 v vin v cc + 0.3 v output leakage current i lo ? 5 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc v high iout = ? ma output low voltage v ol 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih 3 v cc ?0.2 v, 0 v v il 0.2 v.
hm5112805f-6, hm5113805f-6 9 dc characteristics (hm5113805f) hm5113805f -6 parameter symbol min max unit test conditions operating current* 1, * 2 i cc1 220 ma t rc = min standby current i cc2 4 ma ttl interface ras , cas = v ih dout = high-z 1 ma cmos interface ras , cas 3 v cc ?0.2 v dout = high-z standby current (l-version) i cc2 500 m a cmos interface ras , cas 3 v cc ?0.2 v dout = high-z ras -only refresh current* 2 i cc3 220 ma t rc = min standby current* 1 i cc5 ?0ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 220 ma t rc = min edo page mode current* 1, * 3 i cc7 200 ma ras = v il , cas cycle, t hpc = t hpc min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 2.5 ma cmos interface dout = high-z cbr refresh: t rc = 15.6 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 1.6 ma cmos interface ras , cas 0.2 v dout = high-z input leakage current i li ? 5 m a 0 v vin v cc + 0.3 v output leakage current i lo ? 5 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc v high iout = ? ma output low voltage v ol 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih 3 v cc ?0.2 v, 0 v v il 0.2 v.
hm5112805f-6, hm5113805f-6 10 capacitance (ta = 25?c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 7 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 8 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras and cas = v ih to disable dout.
hm5112805f-6, hm5113805f-6 11 ac characteristics (ta = 0 to +70?c, v cc = 3.3 v 0.3 v, v ss = 0 v) * 1, * 2, * 19 test conditions input rise and fall time: 2 ns input pulse levels: v il = 0 v, v ih = 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm5112805f/hm5113805f -6 parameter symbol min max unit notes random read or write cycle time t rc 104 ns ras precharge time t rp 40 ns cas precharge time t cp 10 ns ras pulse width t ras 60 10000 ns cas pulse width t cas 10 10000 ns row address setup time t asr 0ns row address hold time t rah 10 ns column address setup time t asc 0ns column address hold time t cah 10 ns ras to cas delay time t rcd 14 45 ns 3 ras to column address delay time t rad 12 30 ns 4 ras hold time t rsh 15 ns cas hold time t csh 40 ns cas to ras precharge time t crp 5ns oe to din delay time t oed 15 ns 5 oe delay time from din t dzo 0 ns 6 cas delay time from din t dzc 0 ns 6 transition time (rise and fall) t t 250ns7
hm5112805f-6, hm5113805f-6 12 read cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes access time from ras t rac 60 ns 8, 9 access time from cas t cac 15 ns 9, 10, 17 access time from address t aa 30 ns 9, 11, 17 access time from oe t oea ?5ns9 read command setup time t rcs 0ns read command hold time to cas t rch 0 ns 12 read command hold time from ras t rchr 60 ns read command hold time to ras t rrh 0 ns 12 column address to ras lead time t ral 30 ns column address to cas lead time t cal 18 ns cas to output in low-z t clz 0ns output data hold time t oh 3 ns 21 output data hold time from oe t oho 3ns output buffer turn-off time t off 15 ns 13, 21 output buffer turn-off to oe t oez ?5ns13 cas to din delay time t cdd 15 ns 5 output data hold time from ras t ohr 3 ns 21 output buffer turn-off to ras t ofr 15 ns 13, 21 output buffer turn-off to we t wez ?5ns13 we to din delay time t wed 15 ns ras to din delay time t rdd 15 ns
hm5112805f-6, hm5113805f-6 13 write cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes write command setup time t wcs 0 ns 14 write command hold time t wch 10 ns write command pulse width t wp 10 ns write command to ras lead time t rwl 15 ns write command to cas lead time t cwl 10 ns data-in setup time t ds 0 ns 15 data-in hold time t dh 10 ns 15 read-modify-write cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes read-modify-write cycle time t rwc 140 ns ras to we delay time t rwd 79 ns 14 cas to we delay time t cwd 34 ns 14 column address to we delay time t awd 49 ns 14 oe hold time from we t oeh 15 ns refresh cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes cas setup time (cbr refresh cycle) t csr 5ns cas hold time (cbr refresh cycle) t chr 10 ns we setup time (cbr refresh cycle) t wrp 0ns we hold time (cbr refresh cycle) t wrh 10 ns ras precharge to cas hold time t rpc 5ns
hm5112805f-6, hm5113805f-6 14 edo page mode cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes edo page mode cycle time t hpc 25 ns 20 edo page mode ras pulse width t rasp 100000 ns 16 access time from cas precharge t cpa 35 ns 9, 17 ras hold time from cas precharge t cprh 35 ns output data hold time from cas low t doh 3 ns 9, 22 cas hold time referred oe t col 10 ns cas to oe setup time t cop 5ns read command hold time from cas precharge t rchc 35 ns write pulse width during cas precharge t wpe 10 ns oe precharge time t oep 10 ns edo page mode read-modify-write cycle hm5112805f/hm5113805f -6 parameter symbol min max unit notes edo page mode read-modify-write cycle time t hprwc 68 ns we delay time from cas precharge t cpw 54 ns 14 refresh (hm5112805f) parameter symbol max unit notes refresh period t ref 64 ms 8192 cycles refresh period (l-version) t ref 64 ms 8192 cycles refresh (hm5113805f) parameter symbol max unit notes refresh period t ref 64 ms 4096 cycles refresh period (l-version) t ref 64 ms 4096 cycles
hm5112805f-6, hm5113805f-6 15 self refresh mode (l-version) hm5112805fl/hm5113805fl -6 parameter symbol min max unit notes ras pulse width (self refresh) t rass 100 m s25 ras precharge time (self refresh) t rps 110 ns 25 cas hold time (self refresh) t chs ?0 ns notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, than the access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max), t oez (max), t wez (max) and t ofr (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t ds and t dh are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level.
hm5112805f-6, hm5113805f-6 16 20. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 21. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh and between t ofr and t off . 22. t doh defines the time at which the output level go cross. v ol = 0.8 v, v oh = 2.0 v of output timing reference level. 23. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. enter self refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after exiting from self refresh mode. 24. in case of entering from ras -only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 23. 25 at t rass > 100 m s, self refresh mode is activated, and not activated at t rass < 10 m s. it is undefined within the range of 10 m s t rass 100 m s. for t rass 3 10 m s, it is necessary to satisfy t rps . 26. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm5112805f-6, hm5113805f-6 17 timing waveforms * 26 read cycle ras address we dout oe din t rc row column t rcs t rch t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez cas t rdd t wed t ofr t ohr t wez t ras t cas t rp t csh t rcd t rsh t crp t t t rad t ral t cal t asr t asc t cah t rchr t rrh t rah
hm5112805f-6, hm5113805f-6 18 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hm5112805f-6, hm5113805f-6 19 delayed write cycle * 18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t oep t clz t oez high-z invalid dout din high-z
hm5112805f-6, hm5113805f-6 20 read-modify-write cycle * 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas t oep
hm5112805f-6, hm5113805f-6 21 ras -only refresh cycle ! ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr
hm5112805f-6, hm5113805f-6 22 cas -before- ras refresh cycle ras cas we address dout high-z t off t ofr t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
hm5112805f-6, hm5113805f-6 23 hidden refresh cycle din oe dout we address ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t cdd t dzc t oed t oez t oho t off t oh t cac t aa t rac t clz dout column row t oea high-z t rch t rrh cas t wed t rdd t wez t ofr t ohr t rcs t dzo
hm5112805f-6, hm5113805f-6 24 edo page mode read cycle (1)
din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed oho doh rch t wpe t rchr t cal t cal t cal t rsh t rchc cpa asc t oep t oep
hm5112805f-6, hm5113805f-6 25 edo page mode read cycle (2)
din oe we address t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t doh t t oez t t oez t aa t cac t cop t asr t rah t t cah t asc t cah t cah t asc t cah t asc t wed t ral dout 2 dout 4 dout 1 t rcs t oho t oea dzo t oed t doh t cac t rchc cpa asc ras cas t cp t cp t cp t t t rch t rrh t rasp t rp t cas t cas t cas t csh t hpc t hpc t hpc crp t t cas t cal t cal t cal t cal t rsh dout dout 3 dout 2 oho oea t cpa column 2 column 1 row column 3 column 4 t oep t oep
hm5112805f-6, hm5113805f-6 26 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hm5112805f-6, hm5113805f-6 27 edo page mode delayed write cycle * 18 ! " we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas t oep t oep t oep
hm5112805f-6, hm5113805f-6 28 edo page mode read-modify-write cycle * 18 " # we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oep t oep t oep t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hm5112805f-6, hm5113805f-6 29 edo page mode mix cycle (1)* 20 oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t cwl t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t oep t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din
hm5112805f-6, hm5113805f-6 30 edo page mode mix cycle (2) * 20 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas t cwl dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa t oep t oep cop
hm5112805f-6, hm5113805f-6 31 self refresh cycle (l-version)* 23, 24, 25 $ % & + , ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z cas t wrp t wrh we
hm5112805f-6, hm5113805f-6 32 package dimensions hm5112805ftd/fltd hm5113805ftd/fltd (ttp-32df) hitachi code jedec eiaj weight (reference value) ttp-32df 0.54 g unit: mm *dimension including the plating thickness base material dimension 1.27 0.21 m *0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.05 0.05 *0.12 0.05 11.76 0.20 0.50 0.10 0.45 1.15 max 0.80 0.40 0.06 0.10 0.04
hm5112805f-6, hm5113805f-6 33 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/index.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hm5112805f-6, hm5113805f-6 34 revision record rev. date contents of modification drawn by approved by 0.0 may. 19, 1999 initial issue m. kawamura m. mishima 1.0 nov. 8, 1999 deletion of preliminary m. kawamura y. kasama 2.0 dec. 6, 1999 dc characteristics i cc10 (l-version) max: 2/2 ma to 2.5/2.5 ma m. kawamura y. kasama 3.0 feb. 2, 2000 change of datasheet tittle: hm5112805f series, hm5113805f series to hm5112805f-6, hm5113805f-6

▲Up To Search▲

Price & Availability of HM5112805FLTD-6

	To Download HM5112805FLTD-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .